The present invention relates generally to electronic design automation (EDA) tools, and, more particularly, to an EDA tool capable of modifying an integrated circuit design for reduced dynamic power consumption.
Integrated circuits (ICs), such as systems-on-chip (SoCs) include combinational and sequential logic elements including flip-flops and latches that operate based on toggling of a clock signal received by the SoC. The flip-flops and latches consume a significant amount of power. The outputs of the flip-flops and latches change at every edge of the clock signal, which adds to the power consumption because the power consumed is directly proportional to operational voltage and operational frequency of the clock signal. The magnitude of the power consumed can be calculated using the equation (1):Power consumed=α*C*V2*F  (1)where,α=switching factor of the clock signal,C=load capacitance that is charged or discharged during each cycle of the clock signal,V=operational voltage of the SoC, andF=operational frequency of the clock signal.Power consumption may be reduced by controlling the above parameters. Reducing the operational frequency of the clock signal affects circuit performance, while reducing the operational voltage increases propagation delays of the logic circuits. The switching factor (α) and the capacitance (C) can be reduced by disabling the clock signal when the flip-flops and the latches are idle.
One technique for disabling the clock signal is to gate the clock signal using a clock gating cell, which saves dynamic functional power. Clock gating cells are generally inserted into the design during the RTL design synthesis stage. Groups of flip-flops that share a common enable control signal or have a common enable condition are selected during the RTL design synthesis state. The enable control signal is used to control a clock gating cell that is connected to clock input terminals of the flip-flops of the selected group of flip-flops. When the enable control signal is low, the dynamic power consumption across the selected group of flip-flops is zero, which results in a considerable reduction in power consumption.
Typically, RTL clock gating is of two types: latch-free and latch-based. In latch-free clock gating, AND and OR gates are used to gate the clock signal when the selected group of flip-flops are idle. The enable control signal for the selected group of flip-flops and the clock signal are input to the AND gate or the OR gate. Based on the logic state of the enable control signal, the gate generates a gated clock signal that is provided to the clock input terminals of the flip-flops. The AND gate generates a logic low gated clock signal and the OR gate generates a logic high gated clock signal when the enable control signal is low. However, when the logic state of the enable control signal toggles between two pulses of the clock signal, the gated clock signal is either terminated prematurely or generates multiple clock pulses with indeterminate time periods. Hence, latch-free clock gating is not preferred for clock gating of flip-flops that use a single clock signal.
In latch-based clock gating, the enable control signal is provided to a data input terminal of a level-sensitive latch. The latch also receives the clock signal at its clock input terminal. An output of the latch is provided to either an AND gate or an OR gate. The gate also receives the clock signal and outputs the gated clock signal at low and high states, respectively, when the enable control signal is low. The latch captures the logic state of the enable control signal and holds the captured logic state until a complete pulse of the gated clock signal is generated. Hence, the logic state of the enable control signal must be stable only at the rising edge of the clock signal for the gated clock signal to be generated accurately.
Modern EDA tools have built-in functionality to choose the AND-type latch-based clock gating cells for gating the clock signal received by the selected group of flip-flops. A flip-flop includes a master latch and a slave latch. A positive-edge triggered flip-flop has a low-active master latch and a high-active slave latch, and a negative-edge triggered flip-flop has a high-active master latch and a low-active slave latch. When the selected group of flip-flops includes positive-edge triggered flip-flops and the AND-type latch-based clock gating cell is used, the master latch of each positive-edge triggered flip-flop of the selected group receives the gated clock signal at logic low state. As a result, the master latch of each positive-edge triggered flip-flop is set in a transparent mode. Hence, any change at a data input terminal of the master latch of each positive-edge triggered flip-flop is reflected at an output terminal of the master latch, thereby increasing internal dynamic power consumption of the positive-edge triggered flip-flops during idle state.
FIG. 1 is a schematic block diagram of a conventional system 100 for gating a clock signal. The system 100 includes a positive-edge triggered D flip-flop 102, a multiplexer 104, and an AND-type latch-based clock gating cell 106. The clock gating cell 106 includes a D latch 108 and an AND gate 110. A data input terminal of the D latch 108 receives an enable control signal and a clock input terminal of the latch 108 receives the clock signal. A first input terminal of the AND gate 110 is connected to an output terminal of the D latch 108 for receiving the enable control signal and a second input terminal of the AND gate 110 receives the clock signal. The AND gate 110 outputs a gated clock signal at its output terminal. A first input terminal of the multiplexer 104 is connected to an output terminal of the D flip-flop 102 for receiving an output signal of the D flip-flop 102 and a second input terminal of the multiplexer 104 receives a data input signal. A select input terminal of the multiplexer 104 receives the enable control signal. A data input terminal of the D flip-flop 102 is connected to an output terminal of the multiplexer 104 for receiving one of the data input signal and the output signal of the D flip-flop 102. A clock input terminal of the D flip-flop 102 is connected to the output terminal of the AND gate 110 for receiving the gated clock signal.
When the enable control signal and the clock signal are at low, the D latch 108 outputs a low enable control signal. The AND gate 110 outputs a low gated clock signal upon receiving the low enable control signal at its first input terminal. The multiplexer 104 outputs the output signal of the D flip-flop 102 to the data input terminal of the D flip-flop 102 when the select input terminal of the multiplexer 104 receives the low enable control signal. Hence, a previous state of the D flip-flop 102 is held. As a result, the dynamic power consumption of the D flip-flop 102 is zero during the clock gating period, since there is no change at the data input terminal of the D flip-flop 102 when the enable control signal is low.
When the enable control signal is high and the clock signal is low, the D latch 108 outputs a high enable control signal. A logic state of the gated clock signal toggles based on a logic state of the clock signal when the AND gate 110 receives the high enable control signal at its first input terminal. The multiplexer 104 outputs the data input signal to the data input terminal of the D flip-flop 102 when the select input terminal of the multiplexer 104 receives the logic high enable control signal. Hence, the D flip-flop 102 is set in the transparent mode where any change in the data input terminal of the D flip-flop 102 is reflected at its output terminal. However, a SoC includes thousands of positive-edge triggered flip-flops and each requires a dedicated multiplexer connected at its data input terminal, which drastically increases chip area.
Therefore, it would be advantageous to have a system for reducing dynamic power consumption yet requires few design changes and does not drastically increase chip area.